Modelsim altera starter edition 10.3d
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- #MODELSIM ALTERA STARTER EDITION 10.3D SERIAL#
- #MODELSIM ALTERA STARTER EDITION 10.3D MANUAL#
- #MODELSIM ALTERA STARTER EDITION 10.3D CODE#
Design FileĪrria V Custom PHY simple way to auto enable serial loopback design example QII v13.1 (QAR)Īrria V Custom PHY simple way to manually enable serial
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#MODELSIM ALTERA STARTER EDITION 10.3D CODE#
You should code your own control logics to enable the serial loopback. Note that these designs should serve as a quick reference to enable serial loopback. Write a value of '1' to the source in the ISSP Editor to enable the internal serial loopback.
#MODELSIM ALTERA STARTER EDITION 10.3D MANUAL#
As for the manual enabled design example, after downloading the SOF file, you will need to launch the In-System Source and Probe Editor at the Quartus II -> Tools menu. The designs have been tested with Arria V Starter kit.įor the auto enabled design example, once the receiver's rx_is_lockedtoref signal goes high, the serial loopback will be enabled. There are two design examples attached - one is with auto internal serial loopback enabled and another is manual enabled through In-System Source and Probe (ISSP). By having the serial loopback in place, it allows you to focus on the transceiver blocks debugging and get away from external factors ie signal integrity. These basic design examples demonstrates simple ways to enable internal serial loopback in Arria V Custom PHY to facilitate issue debugging. Design SpecificationsĪrria V Custom PHY simple ways to enable internal serial loopback design examples Overview Note that you should create your dynamic reconfiguration state machine as the controls are done in test bench in the example.Īrria V Native PHY with data rate change using TX PLL switching dynamic reconfiguration design examp. There is no TX PLL reconfiguration required in this case. The design show reconfiguration from 800Mbps to 1600Mbps after achieving synchronization. The design also come with example test bench and TCL file to run simulation in Modelsim for reference. The purpose of this design example is to assist users to have quick start with the Arria V transceivers TX local divider dynamic reconfiguration using MIF mode as well as manual alignment. This basic design example with Modelsim simulation demonstrates the implementing of Arria V Native PHY with manual alignment and data rate change with TX local divider dynamic reconfiguration in Quartus Prime 15.1. Native PHY IP, Transceiver Reconfiguration Controller, Transceiver PHY Reset ControllerĪrria V Native PHY with manual alignment and data rate change with TX local divider dynamic reconfiguration design example in Quartus Prime 15.1 Overview The table below lists the specifications for this design: Attribute Type "simulate" to start simulation Design FileĪrria V Native PHY with manual alignment, 8b10b enabled and 20 bit PCS-PMA width design example QII. Change the Modelsim directory to the unzipped folderĥ. Note that you should create your word alignment controller as the controls are done in test bench in the example.Ģ. The design consist of only one transceiver channel with fixed 16 bits data pattern. The purpose of this design example is to assist users to have quick start with the Arria V transceivers. This basic design example with Modelsim simulation demonstrates the implementing of Arria V Native PHY with manual alignment, 8b10b enabled and 20 bit PCS-PMA. Arria V Transceiver PHY Basic Design ExamplesĪrria V Native PHY with manual alignment, 8b10b enabled and 20 bit PCS-PMA width design example